Cadence Donates Technology to IEEE to Enhance SystemVerilog Usability; Data Types and IP Encryption to Be Part of Initial IEEE SystemVerilog Standard
SAN JOSE, Calif.—(BUSINESS WIRE)—Feb. 14, 2005—
Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN)
today announced that it has donated SystemVerilog data type and
intellectual property (IP) encryption technology to the IEEE P1800
Working Group to enhance SystemVerilog usability. The IEEE P1800
Working Group will incorporate the Cadence(R) technology in the first
release of the SystemVerilog standard, due later this year. These
donations enhance the data types that are currently available in
SystemVerilog and enable existing encryption technology to be used to
encrypt SystemVerilog code, resulting in enhanced language efficiency
and usability.
SystemVerilog enables hardware designers to build on the strengths
of Verilog(R) to help address the challenges in design and
verification of next-generation system-on-chip (SoC) devices. The
Cadence donation provides enhanced data types that raise the level of
abstraction in SystemVerilog, enhancing designer productivity and
language usability.
"Cadence has leveraged its leadership in language design and
hardware implementation, and is providing valuable technology to
designers," said Kevin Silver, vice president marketing for Denali
Software, Inc. "Cadence's support for SystemVerilog ensures that the
Verilog language will remain a unified industry standard. This
unification is very important to users.
"Providing a single language for additional design and
verification capabilities reduces the cost of tools and education, and
makes it easier for the new technology to be adopted."
The adoption of the Cadence customer-proven IP encryption
technology will allow secure distribution of IP blocks in the standard
language. The technology is a major enabler for IP-based SoC design
and solves a significant industry problem by providing a standard
mechanism for IP protection.
"We've been successfully using this encryption technology with the
Incisive functional verification platform using VHDL, and are looking
forward to seeing this capability standardized on by all hardware
description languages, including SystemVerilog," said Reno Sanchez,
director, Microprocessor Center of Excellence, Xilinx. "This
encryption technology will make it easier for us to protect our IP as
well as help our customers gain access to a broad portfolio of
high-value IP, and do so within an industry standards-based protocol."
"In response to our customers' needs, Cadence is driving support
for a single Verilog standard that will give users the benefits of
open interoperability, exemplified by our recent donations to the
IEEE," said Victor Berman, director of Language Standards at Cadence.
"Our design and verification platforms, especially the Incisive
functional verification platform, are built around open standards that
offer customers the flexibility and language choice needed to optimize
their verification methodology."
As the initial developer of the Verilog language, Cadence now
provides design and verification platform support for SystemVerilog,
VHDL, Verilog, PSL/OVL, SystemC, Verilog-AMS and VHDL-AMS. Customers
can efficiently run SystemC to verify system function, SystemVerilog
and Verilog to verify gate implementation and timing, VHDL for
compatibility, PSL for complete assertion-based verification, and AMS
for mixed-signal designs. All of these languages now run inside a
single simulation interface, allowing customers to use any combination
for design and verification to improve language interoperability.
Cadence technologies supporting SystemVerilog include the
Encounter(TM) digital IC design platform and Incisive(TM) functional
verification platform, providing customers a powerful option for
design, synthesis, formal verification, and acceleration/emulation.
For more information, visit
http://www.cadence.com/partners/languages/languages.aspx.
About Cadence
Cadence is the world's largest supplier of electronic design
technologies and engineering services. Cadence products and services
are used to accelerate and manage the design of semiconductors,
computer systems, networking equipment, telecommunications equipment,
consumer electronics, and other electronics based products. With
approximately 4,900 employees and 2004 revenues of approximately $1.2
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and trades on both the New York Stock Exchange and Nasdaq
under the symbol CDN. More information is available at
www.cadence.com.
Cadence, the Cadence logo and Verilog are registered trademarks of
Cadence Design Systems, Inc. Encounter and Incisive are trademarks of
Cadence Design Systems, Inc. All other trademarks are the property of
their respective owners.
Contact:
Cadence Design Systems, Inc.
Michael Fournell, 408-428-5135
fournell@cadence.com
